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5007142 Add ntohll and htonll to sys/byteorder.h
6717509 Need to use bswap/bswapq for byte swap of 64-bit integer on x32/x64
PSARC 2008/474
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--- old/usr/src/uts/intel/amd64/ml/amd64.il
+++ new/usr/src/uts/intel/amd64/ml/amd64.il
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 - * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
22 + * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 -#pragma ident "%Z%%M% %I% %E% SMI"
27 -
28 26 /
29 27 / In-line functions for amd64 kernels.
30 28 /
31 29
32 30 /
33 31 / return current thread pointer
34 32 /
35 33 / NOTE: the "0x18" should be replaced by the computed value of the
36 34 / offset of "cpu_thread" from the beginning of the struct cpu.
37 35 / Including "assym.h" does not work, however, since that stuff
38 36 / is PSM-specific and is only visible to the 'unix' build anyway.
39 37 / Same with current cpu pointer, where "0xc" should be replaced
40 38 / by the computed value of the offset of "cpu_self".
41 39 / Ugh -- what a disaster.
42 40 /
43 41 .inline threadp,0
44 42 movq %gs:0x18, %rax
45 43 .end
46 44
47 45 /
48 46 / return current cpu pointer
49 47 /
50 48 .inline curcpup,0
51 49 movq %gs:0x10, %rax
52 50 .end
53 51
54 52 /
55 53 / return caller
56 54 /
57 55 .inline caller,0
58 56 movq 8(%rbp), %rax
59 57 .end
60 58
61 59 /
62 60 / convert ipl to spl. This is the identity function for i86
63 61 /
64 62 .inline ipltospl,0
65 63 movq %rdi, %rax
66 64 .end
67 65
68 66 /
69 67 / find the low order bit in a word
70 68 /
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71 69 .inline lowbit,4
72 70 movq $-1, %rax
73 71 bsfq %rdi, %rax
74 72 incq %rax
75 73 .end
76 74
77 75 /
78 76 / Networking byte order functions (too bad, Intel has the wrong byte order)
79 77 /
80 78
79 + .inline htonll,4
80 + movq %rdi, %rax
81 + bswapq %rax
82 + .end
83 +
84 + .inline ntohll,4
85 + movq %rdi, %rax
86 + bswapq %rax
87 + .end
88 +
81 89 .inline htonl,4
82 90 movl %edi, %eax
83 91 bswap %eax
84 92 .end
85 93
86 94 .inline ntohl,4
87 95 movl %edi, %eax
88 96 bswap %eax
89 97 .end
90 98
91 99 .inline htons,4
92 100 movl %edi, %eax
93 101 bswap %eax
94 102 shrl $16, %eax
95 103 .end
96 104
97 105 .inline ntohs,4
98 106 movl %edi, %eax
99 107 bswap %eax
100 108 shrl $16, %eax
101 109 .end
102 110
103 111 /*
104 112 * multiply two long numbers and yield a u_lonlong_t result
105 113 * Provided to manipulate hrtime_t values.
106 114 */
107 115 /* XX64 These don't work correctly with SOS9 build 13.0 yet
108 116 .inline mul32, 8
109 117 xorl %edx, %edx
110 118 movl %edi, %eax
111 119 mull %esi
112 120 shlq $32, %rdx
113 121 orq %rdx, %rax
114 122 ret
115 123 .end
116 124 */
117 125 /*
118 126 * Unlock hres_lock and increment the count value. (See clock.h)
119 127 */
120 128 .inline unlock_hres_lock, 0
121 129 lock
122 130 incl hres_lock
123 131 .end
124 132
125 133 .inline atomic_orb,8
126 134 movl %esi, %eax
127 135 lock
128 136 orb %al,(%rdi)
129 137 .end
130 138
131 139 .inline atomic_andb,8
132 140 movl %esi, %eax
133 141 lock
134 142 andb %al,(%rdi)
135 143 .end
136 144
137 145 /*
138 146 * atomic inc/dec operations.
139 147 * void atomic_inc16(uint16_t *addr) { ++*addr; }
140 148 * void atomic_dec16(uint16_t *addr) { --*addr; }
141 149 */
142 150 .inline atomic_inc16,4
143 151 lock
144 152 incw (%rdi)
145 153 .end
146 154
147 155 .inline atomic_dec16,4
148 156 lock
149 157 decw (%rdi)
150 158 .end
151 159
152 160 /*
153 161 * atomic bit clear
154 162 */
155 163 .inline atomic_btr32,8
156 164 lock
157 165 btrl %esi, (%rdi)
158 166 setc %al
159 167 .end
160 168
161 169 /*
162 170 * Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
163 171 * a hint that the code sequence is a busy spin-wait loop. Without a pause
164 172 * instruction in these loops, the P4 Xeon processor may suffer a severe
165 173 * penalty when exiting the loop because the processor detects a possible
166 174 * memory violation. Inserting the pause instruction significantly reduces
167 175 * the likelihood of a memory order violation, improving performance.
168 176 * The pause instruction is a NOP on all other IA-32 processors.
169 177 */
170 178 .inline ht_pause, 0
171 179 pause
172 180 .end
173 181
174 182 /*
175 183 * inlines for update_sregs().
176 184 */
177 185 .inline __set_ds, 0
178 186 movw %di, %ds
179 187 .end
180 188
181 189 .inline __set_es, 0
182 190 movw %di, %es
183 191 .end
184 192
185 193 .inline __set_fs, 0
186 194 movw %di, %fs
187 195 .end
188 196
189 197 .inline __set_gs, 0
190 198 movw %di, %gs
191 199 .end
192 200
193 201 /*
194 202 * OPTERON_ERRATUM_88 requires mfence
195 203 */
196 204 .inline __swapgs, 0
197 205 mfence
198 206 swapgs
199 207 .end
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