1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26 
  27 #pragma ident   "%Z%%M% %I%     %E% SMI"
  28 
  29 /
  30 / Inline functions for i386 kernels.
  31 /       Shared between all x86 platform variants.
  32 /
  33 
  34 /
  35 / return current thread pointer
  36 /
  37 / NOTE: the "0x10" should be replaced by the computed value of the
  38 /       offset of "cpu_thread" from the beginning of the struct cpu.
  39 /       Including "assym.h" does not work, however, since that stuff
  40 /       is PSM-specific and is only visible to the 'unix' build anyway.
  41 /       Same with current cpu pointer, where "0xc" should be replaced
  42 /       by the computed value of the offset of "cpu_self".
  43 /       Ugh -- what a disaster.
  44 /
  45         .inline threadp,0
  46         movl    %gs:0x10, %eax
  47         .end
  48 
  49 /
  50 / return current cpu pointer
  51 /
  52         .inline curcpup,0
  53         movl    %gs:0xc, %eax
  54         .end
  55 
  56 /
  57 / return caller
  58 /
  59         .inline caller,0
  60         movl    4(%ebp), %eax
  61         .end
  62 
  63 /
  64 / convert ipl to spl.  This is the identity function for i86
  65 /
  66         .inline ipltospl,0
  67         movl    (%esp), %eax
  68         .end
  69 
  70 /
  71 / find the low order bit in a word
  72 /
  73         .inline lowbit,4
  74         movl    $-1, %eax
  75         bsfl    (%esp), %eax
  76         incl    %eax
  77         .end
  78 
  79 /
  80 / find the high order bit in a word
  81 /
  82         .inline highbit,4
  83         movl    $-1, %eax
  84         bsrl    (%esp), %eax
  85         incl    %eax
  86         .end
  87 
  88 /
  89 / Networking byte order functions (too bad, Intel has the wrong byte order)
  90 /
  91         .inline htonl,4
  92         movl    (%esp), %eax
  93         bswap   %eax
  94         .end
  95 
  96         .inline ntohl,4
  97         movl    (%esp), %eax
  98         bswap   %eax
  99         .end
 100 
 101         .inline htons,4
 102         movl    (%esp), %eax
 103         bswap   %eax
 104         shrl    $16, %eax
 105         .end
 106 
 107         .inline ntohs,4
 108         movl    (%esp), %eax
 109         bswap   %eax
 110         shrl    $16, %eax
 111         .end
 112 
 113 /*
 114  * multiply two long numbers and yield a u_longlong_t result
 115  * Provided to manipulate hrtime_t values.
 116  */
 117         .inline mul32, 8
 118         movl    4(%esp), %eax
 119         movl    (%esp), %ecx
 120         mull    %ecx
 121         .end
 122 
 123 /*
 124  * Unlock hres_lock and increment the count value. (See clock.h)
 125  */
 126         .inline unlock_hres_lock, 0
 127         lock
 128         incl    hres_lock
 129         .end
 130 
 131         .inline atomic_orb,8
 132         movl    (%esp), %eax
 133         movl    4(%esp), %edx
 134         lock
 135         orb     %dl,(%eax)
 136         .end
 137 
 138         .inline atomic_andb,8
 139         movl    (%esp), %eax
 140         movl    4(%esp), %edx
 141         lock
 142         andb    %dl,(%eax)
 143         .end
 144 
 145 /*
 146  * atomic inc/dec operations.
 147  *      void atomic_inc16(uint16_t *addr) { ++*addr; }
 148  *      void atomic_dec16(uint16_t *addr) { --*addr; }
 149  */
 150         .inline atomic_inc16,4
 151         movl    (%esp), %eax
 152         lock
 153         incw    (%eax)
 154         .end
 155 
 156         .inline atomic_dec16,4
 157         movl    (%esp), %eax
 158         lock
 159         decw    (%eax)
 160         .end
 161 
 162 /*
 163  * Call the pause instruction.  To the Pentium 4 Xeon processor, it acts as
 164  * a hint that the code sequence is a busy spin-wait loop.  Without a pause
 165  * instruction in these loops, the P4 Xeon processor may suffer a severe
 166  * penalty when exiting the loop because the processor detects a possible
 167  * memory violation.  Inserting the pause instruction significantly reduces
 168  * the likelihood of a memory order violation, improving performance.
 169  * The pause instruction is a NOP on all other IA-32 processors.
 170  */
 171         .inline ht_pause, 0
 172         rep                     / our compiler doesn't support "pause" yet,
 173         nop                     / so we're using "F3 90" opcode directly
 174         .end