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5007142 Add ntohll and htonll to sys/byteorder.h
6717509 Need to use bswap/bswapq for byte swap of 64-bit integer on x32/x64
PSARC 2008/474
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--- old/usr/src/uts/intel/ia32/ml/ia32.il
+++ new/usr/src/uts/intel/ia32/ml/ia32.il
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
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13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
23 + * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 -#pragma ident "%Z%%M% %I% %E% SMI"
28 -
29 27 /
30 28 / Inline functions for i386 kernels.
31 29 / Shared between all x86 platform variants.
32 30 /
33 31
34 32 /
35 33 / return current thread pointer
36 34 /
37 35 / NOTE: the "0x10" should be replaced by the computed value of the
38 36 / offset of "cpu_thread" from the beginning of the struct cpu.
39 37 / Including "assym.h" does not work, however, since that stuff
40 38 / is PSM-specific and is only visible to the 'unix' build anyway.
41 39 / Same with current cpu pointer, where "0xc" should be replaced
42 40 / by the computed value of the offset of "cpu_self".
43 41 / Ugh -- what a disaster.
44 42 /
45 43 .inline threadp,0
46 44 movl %gs:0x10, %eax
47 45 .end
48 46
49 47 /
50 48 / return current cpu pointer
51 49 /
52 50 .inline curcpup,0
53 51 movl %gs:0xc, %eax
54 52 .end
55 53
56 54 /
57 55 / return caller
58 56 /
59 57 .inline caller,0
60 58 movl 4(%ebp), %eax
61 59 .end
62 60
63 61 /
64 62 / convert ipl to spl. This is the identity function for i86
65 63 /
66 64 .inline ipltospl,0
67 65 movl (%esp), %eax
68 66 .end
69 67
70 68 /
71 69 / find the low order bit in a word
72 70 /
73 71 .inline lowbit,4
74 72 movl $-1, %eax
75 73 bsfl (%esp), %eax
76 74 incl %eax
77 75 .end
78 76
79 77 /
80 78 / find the high order bit in a word
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81 79 /
82 80 .inline highbit,4
83 81 movl $-1, %eax
84 82 bsrl (%esp), %eax
85 83 incl %eax
86 84 .end
87 85
88 86 /
89 87 / Networking byte order functions (too bad, Intel has the wrong byte order)
90 88 /
89 + .inline htonll,4
90 + movl (%esp), %edx
91 + movl 4(%esp), %eax
92 + bswap %edx
93 + bswap %eax
94 + .end
95 +
96 + .inline ntohll,4
97 + movl (%esp), %edx
98 + movl 4(%esp), %eax
99 + bswap %edx
100 + bswap %eax
101 + .end
102 +
91 103 .inline htonl,4
92 104 movl (%esp), %eax
93 105 bswap %eax
94 106 .end
95 107
96 108 .inline ntohl,4
97 109 movl (%esp), %eax
98 110 bswap %eax
99 111 .end
100 112
101 113 .inline htons,4
102 114 movl (%esp), %eax
103 115 bswap %eax
104 116 shrl $16, %eax
105 117 .end
106 118
107 119 .inline ntohs,4
108 120 movl (%esp), %eax
109 121 bswap %eax
110 122 shrl $16, %eax
111 123 .end
112 124
113 125 /*
114 126 * multiply two long numbers and yield a u_longlong_t result
115 127 * Provided to manipulate hrtime_t values.
116 128 */
117 129 .inline mul32, 8
118 130 movl 4(%esp), %eax
119 131 movl (%esp), %ecx
120 132 mull %ecx
121 133 .end
122 134
123 135 /*
124 136 * Unlock hres_lock and increment the count value. (See clock.h)
125 137 */
126 138 .inline unlock_hres_lock, 0
127 139 lock
128 140 incl hres_lock
129 141 .end
130 142
131 143 .inline atomic_orb,8
132 144 movl (%esp), %eax
133 145 movl 4(%esp), %edx
134 146 lock
135 147 orb %dl,(%eax)
136 148 .end
137 149
138 150 .inline atomic_andb,8
139 151 movl (%esp), %eax
140 152 movl 4(%esp), %edx
141 153 lock
142 154 andb %dl,(%eax)
143 155 .end
144 156
145 157 /*
146 158 * atomic inc/dec operations.
147 159 * void atomic_inc16(uint16_t *addr) { ++*addr; }
148 160 * void atomic_dec16(uint16_t *addr) { --*addr; }
149 161 */
150 162 .inline atomic_inc16,4
151 163 movl (%esp), %eax
152 164 lock
153 165 incw (%eax)
154 166 .end
155 167
156 168 .inline atomic_dec16,4
157 169 movl (%esp), %eax
158 170 lock
159 171 decw (%eax)
160 172 .end
161 173
162 174 /*
163 175 * Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
164 176 * a hint that the code sequence is a busy spin-wait loop. Without a pause
165 177 * instruction in these loops, the P4 Xeon processor may suffer a severe
166 178 * penalty when exiting the loop because the processor detects a possible
167 179 * memory violation. Inserting the pause instruction significantly reduces
168 180 * the likelihood of a memory order violation, improving performance.
169 181 * The pause instruction is a NOP on all other IA-32 processors.
170 182 */
171 183 .inline ht_pause, 0
172 184 rep / our compiler doesn't support "pause" yet,
173 185 nop / so we're using "F3 90" opcode directly
174 186 .end
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